Fast cell switching technique, the so called ATM, after the English acronym "Asynchronous Transfer Mode", are playing an increasingly important part in the integrated switching of digital flows of services for the transmission of speech, video and data signals with different bandwidth requirements and traffic characteristics.
The ATM technique is to date universally considered the solution for implementing broadband ISDN, the so-called B-ISDN. It is an efficient fast-packet switching technique dealing with predetermined length entities, referred to as cells, and combining the advantages offered by conventional circuit and packet switching techniques.
Hence such a technique allows, thanks to the flexibility inherent in packet switching, processing of any type of information through a single switching technique within an integrated network structure which can be independent of bit rate, and hence can be capable of dealing with variable bit-rate connections.
The resources offered by the switching system are not strictly dedicated to a single call for its whole duration, as in circuit switching systems, but are used only at the instant at which there is the necessity of transmitting information.
As is known, this technique requires that information relevant to the various services be organized in adjacent units or cells with a fixed length of about 400 bits. They are composed of an information field and of a header field, the so called label, which carries the information necessary for routing through the connection network and other service information.
The cells are received by line interfaces at the input of a switching node, basically consisting of a control part and of a structure which effects the switching proper. The control part carries out all the high level functions relevant to call processing, to connection network configuration and accessory service control.
Among these functions, one of the most important is the choice of the path through the network. This path is determined at the call establishment and is common to all the cells pertaining to the same call.
The choice is determined in the different cases by the routing constraints through the geographic map and by the occupancy conditions of the connection network of the node.
The structure which carries out the cell switching effects a label conversion, which has only local validity in each trunk between two adjacent nodes, and the routing of the cells pertaining to the same call towards the convenient output through the connection network.
The connection network, which has the task of spatially switching the cells from an input gate to the output gate, must be capable of carrying high-traffic volumes, of the order of some hundred Gbit/s, with low cell loss probability and low call blocking probability. In addition, the connection network must present a minimum transit time and easily adapt to possible modular growth.
It follows that while defining the requirements of an ATM switch, one of the parameters which is to be taken into account is its capacity in terms of bandwidth.
An ATM network in fact will be required to carry very wide band services such as videoconferencing, high bit-rate data transfer, data and image transmission for CAD/CAM applications or multimedia services, and possibly broadcast type services (HDTV).
However, the increasing band request is neither limited, nor stringently dependent on the introduction of new applications and services, for which time and level diffusion are not easy to forecast, but it is due to the increasing speed of local networks (LAN) and to their evolution towards high bit rate integrated LAN which, based on the availability of a physical means such as the optical fiber, are capable of generating high bandwidths that the public network will then be expected to switch.
ATM exchange is then requested to control flows carrying a bandwidth varying from 0 to a maximum which is presently of the order of at least 700 MHz (derived from experimental results referred to in the literature).
Such a requirement is reinforced by estimates which agree in establishing that, in order to allow a better statistic multiplexing, ensure the best performances for burst traffic and provide the minimum connection blocking probability, the switching structure is to dispose of a bandwidth per flow equal to several times that required by the individual service.
In this light the implementation of a switching structure capable of switch inputs at a rate of 700 Mbit/s becomes significant.
A technology which has become increasingly interesting for analogous studies and experimental investigations mentioned in the literature is CMOS technology. Such a technology has been already widely tested and is commercially available at reasonable costs.
The definition of an architecture of an exchange prototype capable of switching ATM flows with a bit rate of the order of 700 Mbit/s could envisage the use of extremely advanced and expensive technologies such as GaAs technologies, some bipolar technologies or least but not last, optical technologies. Such technologies, however, do not possess an integration capability sufficient to realise complex components, such as those now being investigated. In fact ATM switching technique requires high-capacity cell buffers, to which none of the cited technologies, even though with different nuances, appears to be suitable. Besides for a number of the technologies considered the considerable power dissipation is a serious constraint.
Among the known elements for ATM technique, there is the one described in the paper entitled "32.times.32 shared buffer type ATM switch VLSIs for B-ISDN" by Takahiko Kozaki et al, issued in the proceedings of ICC 91 Conference, Denver (USA), Jun. 23-26, 1991.
The described switching module can handle 32 input flows at a bit rate of 150 Mbit/s, supplying as many to the output, and is implemented in CMOS technology. The module architecture is that of a high capacity (4096 cells) shared buffer element, controlled in accordance with a linked list algorithm. By a suitable address control queues are formed within the unique shared memory. The main buffer memory consists of 8 integrated circuits, organized into a bit-slice scheme, according to which each circuit handles a bit of one of the 8-bit input words relevant to the 32 input flows. The control is carried out by two integrated circuits implementing the linked list algorithm and by two FIFO registers which store the addresses available in the main buffer. This switching module, even though it has low power dissipation, since it is implemented in CMOS technology, is rather cumbersome, since it needs the use of a plurality of integrated circuits to be mounted on a printed circuit board.
A solution for converting a 150 Mbit/s 32.times.32 module into a 600 Mbit/s 8.times.8 module is presented in the same paper. Control circuits are modified and some input/output multiplexers and demultiplexers are added, so as to share 600 Mbit/s input flow among four inputs.
A second solution is described in the paper entitled "A 400 Mbit/s 8.times.8 BiCMOS ATM Switch LSI with 128 On-Chip Shared Memory" by Shigeru Tanaka et al., published in the proceedings of ISSCC 91 conference, San Francisco (USA), Feb. 15, 1991. Also in this case the module dealt with is a switch module with shared buffer memory and control carried out according to the list algorithm. It allows building up by a unique integrated circuit a 400 Mbit/s 8.times.8 switching module in a rather expensive BiCMOS technology, a hybrid bipolar and CMOS technology. The parallelism of the 8 input flows is 4 bits and the buffer has a 256 cell capacity. Circuit dissipation is about 6 W at the typical 100 MHz frequency and the input/output gates demand ECL level signals.
Another solution has been presented in Italian patent application n. 68059-A/89, filed on Nov. 30, 1989 in the name of Italtel, Societa Italiana Telecomunicazioni. The switching element described herein operates at 150 Mbit/s and has a structure with shared memory buffer, wherein output queues are controlled by a circuit using CAM (Content Addressable Memory) memories. This type of control structure however poses more serious implementing problems from the technologic point of view, in case of high frequency operation.